1. Field of the Invention
The present invention is directed toward very large scale integrated (VLSI) semiconductor circuit chips and in particular to on-chip test circuits that are provided to maintain and test the functional circuits.
2. Description of the Prior Art
In the prior art it is known that the denser the concentration of functional circuits on a semiconductor chip becomes the more urgent is the need to provide means for the maintenance and testability. The ability to put thousands of circuits on a single chip of silicon offers great potential for reducing power, increasing speed and dramatically reducing the cost of digital circuits. Unfortunately, several serious problems must be solved before this potential can be realized.
A general method of design for testability of VLSI semiconductor circuit chips that is utilized to achieve this goal combines two concepts that are almost independent. This method, called Level Sensitive Scan Design (LSSD) is well known and has been described in several publications including:
A Logic Design Structure for LSI Testability, E. B. Eichelberger, et al, 14th Annual Design Automation Conference, New Orleans, June 1977, pages 462-467;
LSI Chip Design for Testability, E. B. Eichelberger, et al, 1978 IEEE International Solid State Circuits Conference, February 1978, pages 216-217;
Level-Sensitive Scan Design Tests Chips, Boards, System, N. C. Berglund, Electronics, Mar. 15, 1979, pages 108-110.
The first concept is to design the circuitry in its logic structure so that correct operation is not dependent on rise time, fall time, or minimum delay of the individual circuit. The only dependence is that the total delays to a number of levels be less than some known value. The second concept is to design all the internal storage elements (other than memory arrays) so that they can also operate as shift legister latches (SRL). These prior art LSSD, VLSI logic systems or SRLs have been comprised of a plurality of static functional latches, each having an associated static test latch. A static latch is defined as a latch circuit that does not store information as a presence or absence of charge on a capacitor, and consequently, does not require that the latch circuit be refreshed to retain the information. The static latch uses a stationary charge of electricity to retain the present state of the latch as in a configuration of cross-coupled transistor circuits to form a bistable flip-flop.
Because fewer transistors are required to construct a dynamic latch than to construct a static latch and because a large number of latches are formed on a VLSI chip, it is highly desirable to use a dynamic latch to substantially reduce the number of transistors per VLSI chip while performing the same test functions. A dynamic latch is defined as a latch circuit that uses the presence or absence of a charge on a capacitor to store information in which the charge must be recharged or refreshed to retain the information. Although dynamic latches are well known, their use in LSSD VLSI logic systems has not been implemented because the functional latch is essentially a static operating condition device. However, I have determined that because scan operations are always performed in bursts, that is in a series of continuous clock cycles, the scan operation can be performed using dynamic scan latches, even though static functional latch operating conditions exist.